The invention relates to interconnect switches for use in devices and systems.
A multiprocessor system typically includes a plurality of processors. In some multiprocessor systems, a distributed storage or memory system having plural storage or memory modules is employed. The plural processors are capable of executing in parallel, and thus are able to read and write to the memory modules concurrently. As a result, multiple data streams often have to be communicated between the processor nodes, processors and the memory modules, and the processor nodes and distributed storage at the same time.
To improve concurrency, an interconnect switch is employed to interconnect the processor nodes, the processors and the memory modules, and the processor nodes and storage. The interconnect switch has a number of input ports (that usually correspond to the number of processors) and a number of output ports (that usually correspond to the number of memory modules). Typically, the interconnect switch is a crossbar-switching network that couples the input ports to the output ports. The interconnect switch can be implemented in an integrated circuit device such as an application specific integrated circuit (ASIC) device.
In a typical interconnect switch, a first-in-first-out (FIFO) queue is associated with each of the input ports. One of the issues involved in many interconnect switches is blocking of data. When data at the front of an input FIFO queue cannot be forwarded because of contention with another input FIFO queue for the same output port, trailing units of data are blocked from being forwarded to another output port that is available. As a result, a delay is experienced in the communication of data through the interconnect switch. In many high-speed systems, such delays may cause degradation of overall system performance.
In general, a device comprises a plurality of input ports, a plurality of output ports, and an interconnect switch between the input and output ports. The interconnect switch comprises a buffer in a circular queue containing at least one pointer to indicate an available one of plural storage locations in the buffer.
Other or alternative features will become apparent from the following description, from the drawings, and from the claims.